1. Field of the Invention
The invention relates to a buffer chip for actuating one or more connected memory arrangements. The invention also relates to a method for operating a buffer chip for fast memory architectures, such as DDR-III memory chips.
2. Description of the Related Art
For very fast and high-density memory architectures, such as those required for DDR-III memory chips, “buffer chips” are used. The buffer chips allow the “stub bus”, as used today in DDR and DDR-II memory chips, to be replaced and instead a hierarchic bus system in which there are now just point-to-point (P2P) or point-to-2-point (P22P) connections to be used. Such data links allow data transfer rates far beyond one GBPS. In addition, cascading makes it possible to concatenate a large number of buffer chips with one another and to produce memory systems having a very large number of memory chips on just one memory main bus.
The buffer chips usually have one or more memory arrangements connected to them, with the buffer chip receiving commands and data via the P2P data link, parallelizing said commands and data and forwarding them to the appropriate connected memory arrangement. During reading, data is read from the appropriate addressed memory arrangement, serialized and output to the memory controller via the P2P data link.
Particularly in the case of DRAM memory chips, changes from a write operation to a read operation and changes from a read operation to a write operation require different lengths of time, particularly when reading or writing requires that the same memory arrangement be addressed. While changing over from a write operation to a read operation for a memory arrangement necessitates that a waiting time based on the chip parameters TWR (Write Recovery) or TWTR (Write to Read) be taken into account, it is possible to change from a write operation in one memory arrangement to a read operation in another memory arrangement essentially without any waiting time. The result of this is either that the memory controller always uses the long bus turnaround time for every change of access in order to avoid providing additional circuit, for reasons of complexity, or that the memory controller contains a complex logic circuit to provide optimum actuation for all the memory arrangements in the overall system.
The cause of the long bus turnaround times in a memory arrangement is not based on the architecture of the data bus in the system, but rather is linked to the design of the memory chips. This is because it is necessary to ensure that the write data are written safely to the cell array before the activated word line is closed again (TWR) or before new read data can be read from the cell array (TWTR).